If you need urgent consulting help click here
nxp,imx-flexspi
Vendor: NXP Semiconductors
Properties
Top level properties
These property descriptions apply to “nxp,imx-flexspi” nodes themselves. This page also describes child node properties in the following sections.
Properties not inherited from the base binding file.
Name |
Type |
Details |
|---|---|---|
|
|
Enable AHB bufferable write access by setting register field
AHBCR[BUFFERABLEEN].
|
|
|
Enable AHB cacheable read access by setting register field
AHBCR[CACHEABLEEN].
|
|
|
Enable AHB read prefetch by setting register field AHBCR[PREFETCHEN].
|
|
|
Remove burst start address alignment limitation by setting register
field AHBCR[READADDROPT].
|
|
|
Combine port A and port B data pins to support octal mode access by
setting register field MCR0[COMBINATIONEN].
|
|
|
Enable/disable SCKB pad use as SCKA differential clock output,
when enabled, Port B flash access is not available.
|
|
|
Source clock for flash read. See the RXCLKSRC field in register MCR0.
The default corresponds to the reset value of the register field.
Legal values: |
|
|
Clock frequency the SPI peripheral is being driven at, in Hz.
|
|
|
An array of chip select GPIOs to use. Each element
in the array specifies a GPIO. The index in the array
corresponds to the child node that the CS gpio controls.
Example:
spi@... {
cs-gpios = <&gpio0 23 GPIO_ACTIVE_LOW>,
<&gpio1 10 GPIO_ACTIVE_LOW>,
...;
spi-device@0 {
reg = <0>;
...
};
spi-device@1 {
reg = <1>;
...
};
...
};
The child node "spi-device@0" specifies a SPI device with
chip select controller gpio0, pin 23, and devicetree
GPIO flags GPIO_ACTIVE_LOW. Similarly, "spi-device@1" has CS GPIO
controller gpio1, pin 10, and flags GPIO_ACTIVE_LOW. Additional
devices can be configured in the same way.
If unsure about the flags cell, GPIO_ACTIVE_LOW is generally a safe
choice for a typical "CSn" pin. GPIO_ACTIVE_HIGH may be used if
intervening hardware inverts the signal to the peripheral device or
the line itself is active high.
If this property is not defined, no chip select GPIOs are set.
SPI controllers with dedicated CS pins do not need to define
the cs-gpios property.
|
|
|
Pin configuration/s for the first state. Content is specific to the
selected pin controller driver implementation.
|
|
|
Pin configuration/s for the second state. See pinctrl-0.
|
|
|
Pin configuration/s for the third state. See pinctrl-0.
|
|
|
Pin configuration/s for the fourth state. See pinctrl-0.
|
|
|
Pin configuration/s for the fifth state. See pinctrl-0.
|
|
|
Names for the provided states. The number of names needs to match the
number of states.
|
Deprecated properties not inherited from the base binding file.
(None)
Properties inherited from the base binding file, which defines common properties that may be set on many nodes. Not all of these may apply to the “nxp,imx-flexspi” compatible.
Name |
Type |
Details |
|---|---|---|
|
|
register space
This property is required. See Important properties for more information. |
|
|
interrupts for device
This property is required. See Important properties for more information. |
|
|
number of address cells in reg property
This property is required. Constant value: |
|
|
number of size cells in reg property
This property is required. |
|
|
Human readable string describing the device (used as device_get_binding() argument)
This property is required. See Important properties for more information. |
|
|
indicates the operational status of a device
Legal values: See Important properties for more information. |
|
|
compatible strings
This property is required. See Important properties for more information. |
|
|
name of each register space
|
|
|
extended interrupt specifier for device
|
|
|
name of each interrupt
|
|
|
phandle to interrupt controller node
|
|
|
Clock gate information
|
|
|
name of each clock
|
|
|
DMA channels specifiers
|
|
|
Provided names of DMA channel specifiers
|
|
|
IO channels specifiers
|
|
|
Provided names of IO channel specifiers
|
|
|
mailbox / IPM channels specifiers
|
|
|
Provided names of mailbox / IPM channel specifiers
|
|
|
Property to identify that a device can be used as wake up source.
When this property is provided a specific flag is set into the
device that tells the system that the device is capable of
wake up the system.
Wake up capable devices are disabled (interruptions will not wake up
the system) by default but they can be enabled at runtime if necessary.
|
|
|
Power domain the device belongs to.
The device will be notified when the power domain it belongs to is either
suspended or resumed.
|
Child node properties
Name |
Type |
Details |
|---|---|---|
|
|
Chip select interval units, in serial clock cycles. See the
CSINTERVALUNIT field in registers FLASHA1CR0 through FLASHB2CR0. The
default corresponds to the reset value of the register field.
Default value: Legal values: |
|
|
Minimum interval between chip select deassertion and assertion. See the
CSINTERVAL field in registers FLASHA1CR0 through FLASHB2CR0. The
default corresponds to the reset value of the register field.
|
|
|
Chip select setup time, in serial clock cycles. See the TCSS field in
registers FLASHA1CR0 through FLASHB2CR0. The default corresponds to the
reset value of the register field.
Default value: |
|
|
Chip select hold time, in serial clock cycles. See the TCSH field in
registers FLASHA1CR0 through FLASHB2CR0. The default corresponds to the
reset value of the register field.
Default value: |
|
|
Data valid time, in nanoseconds. See the registers DLLACR through
DLLBCR.
|
|
|
Column address bit width. Set to zero if the flash does not support
column address. See the CAS field in registers FLASHA1CR0 through
FLASHB2CR0. The default corresponds to the reset value of the register
field.
|
|
|
Don't transmit the least significant address bit when the flash is word
addressable. See the WA field in registers FLASHA1CR0 through
FLASHB2CR0.
|
|
|
AHB write wait interval units, in AHB clock cycles. See the AWRWAITUNIT
field in registers FLASHA1CR2 through FLASHB2CR2. The default
corresponds to the reset value of the register field.
Default value: Legal values: |
|
|
Time to wait between AHB triggered command sequences. See the AWRWAIT
field in registers FLASHA1CR2 through FLASHB2CR2. The default
corresponds to the reset value of the register field.
|
|
|
register space
This property is required. See Important properties for more information. |
|
|
Maximum clock frequency of device's SPI interface in Hz
This property is required. |
|
|
Human readable string describing the device (used as device_get_binding() argument)
This property is required. See Important properties for more information. |
|
|
Duplex mode, full or half. By default it's always full duplex thus 0
as this is, by far, the most common mode.
Use the macros not the actual enum value, here is the concordance
list (see dt-bindings/spi/spi.h)
0 SPI_FULL_DUPLEX
2048 SPI_HALF_DUPLEX
Legal values: |
|
|
Motorola or TI frame format. By default it's always Motorola's,
thus 0 as this is, by far, the most common format.
Use the macros not the actual enum value, here is the concordance
list (see dt-bindings/spi/spi.h)
0 SPI_FRAME_FORMAT_MOTOROLA
32768 SPI_FRAME_FORMAT_TI
Legal values: |
|
|
indicates the operational status of a device
Legal values: See Important properties for more information. |
|
|
compatible strings
This property is required. See Important properties for more information. |
|
|
name of each register space
|
|
|
interrupts for device
See Important properties for more information. |
|
|
extended interrupt specifier for device
|
|
|
name of each interrupt
|
|
|
phandle to interrupt controller node
|
|
|
Clock gate information
|
|
|
name of each clock
|
|
|
number of address cells in reg property
|
|
|
number of size cells in reg property
|
|
|
DMA channels specifiers
|
|
|
Provided names of DMA channel specifiers
|
|
|
IO channels specifiers
|
|
|
Provided names of IO channel specifiers
|
|
|
mailbox / IPM channels specifiers
|
|
|
Provided names of mailbox / IPM channel specifiers
|
|
|
Property to identify that a device can be used as wake up source.
When this property is provided a specific flag is set into the
device that tells the system that the device is capable of
wake up the system.
Wake up capable devices are disabled (interruptions will not wake up
the system) by default but they can be enabled at runtime if necessary.
|
|
|
Power domain the device belongs to.
The device will be notified when the power domain it belongs to is either
suspended or resumed.
|
|
|
GPIO specifier that controls power to the device.
This property should be provided when the device has a dedicated
switch that controls power to the device. The supply state is
entirely the responsibility of the device driver.
Contrast with vin-supply.
|
|
|
Reference to the regulator that controls power to the device.
The referenced devicetree node must have a regulator compatible.
This property should be provided when device power is supplied
by a shared regulator. The supply state is dependent on the
request status of all devices fed by the regulator.
Contrast with supply-gpios. If both properties are provided
then the regulator must be requested before the supply GPIOS is
set to an active state, and the supply GPIOS must be set to an
inactive state before releasing the regulator.
|
|
|
JEDEC ID as manufacturer ID, memory type, memory density
|
|
|
flash capacity in bits
|
|
|
Contains the 32-bit words in little-endian byte order from the
JESD216 Serial Flash Discoverable Parameters Basic Flash
Parameters table. This provides flash-specific configuration
information in cases were runtime retrieval of SFDP data
is not desired.
|
|
|
Quad Enable Requirements value from JESD216 BFP DW15.
Use NONE if the device detects 1-1-4 and 1-4-4 modes by the
instruction. Use S1B6 if QE is bit 6 of the first status register
byte, and can be configured by reading then writing one byte with
RDSR and WRSR. For other fields see the specification.
Legal values: |
|
|
Enter 4-Byte Addressing value from JESD216 BFP DW16
This property is ignored if the device is configured to use SFDP data
from the sfdp-bfp property (CONFIG_SPI_NOR_SFDP_DEVICETREE) or to read
SFDP properties at runtime (CONFIG_SPI_NOR_SFDP_RUNTIME).
For CONFIG_SPI_NOR_SFDP_MINIMAL this is the 8-bit value from bits 31:24
of DW16 identifying ways a device can be placed into 4-byte addressing
mode. If provided as a non-zero value the driver assumes that 4-byte
addressing is require to access the full address range, and
automatically puts the device into 4-byte address mode when the device
is initialized.
|