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st,stm32h7-rcc
Vendor: STMicroelectronics
Description
STM32 Reset and Clock controller node for STM32H7 devices
This node is in charge of system clock ('SYSCLK') source selection and
System Clock Generation.
Configuring STM32 Reset and Clock controller node:
System clock source should be selected amongst the clock nodes available in "clocks"
node (typically 'clk_hse, clk_csi', 'pll', ...).
As part of this node configuration, SYSCLK frequency should also be defined, using
"clock-frequency" property.
Last, bus clocks (typically HCLK, PCLK1, PCLK2) should be configured using matching
prescaler properties.
Here is an example of correctly configured rcc node:
&rcc {
clocks = <&pll>; /* Set pll as SYSCLK source */
clock-frequency = <DT_FREQ_M(480)>; /* SYSCLK runs at 480MHz */
d1cpre = <1>;
hpre = <1>;
d1ppre = <1>;
d2ppre1 = <1>;
d2ppre2 = <1>;
d3ppre = <1>;
}
Specifying a gated clock:
To specify a gated clock, a peripheral should define a "clocks" property encoded
in the following way:
... {
...
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
...
}
After the phandle referring to rcc node, the first index specifies the registers of
the bus controlling the peripheral and the second index specifies the bit used to
control the peripheral clock in that bus register.
Properties
Properties not inherited from the base binding file.
Name |
Type |
Details |
|---|---|---|
|
|
Number of items to expect in a Clock specifier
This property is required. Constant value: |
|
|
default frequency in Hz for clock output
This property is required. |
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|
D1 Domain, CPU1 clock prescaler. Sets a HCLK frequency (feeding Cortex-M Systick)
lower than SYSCLK frequency (actual core frequency).
Zephyr doesn't make a difference today between these two clocks.
Changing this prescaler is not allowed until it is made possible to
use them independently in Zephyr clock subsystem.
This property is required. Legal values: |
|
|
D2 domain, CPU2 core clock and AHB(1/2/3/4) peripheral prescaler
This property is required. Legal values: |
|
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D1 domain, APB3 peripheral prescaler
This property is required. Legal values: |
|
|
D2 domain, APB1 peripheral prescaler
This property is required. Legal values: |
|
|
D2 domain, APB2 peripheral prescaler
This property is required. Legal values: |
|
|
D3 domain, APB4 peripheral prescaler
This property is required. Legal values: |
Deprecated properties not inherited from the base binding file.
(None)
Properties inherited from the base binding file, which defines common properties that may be set on many nodes. Not all of these may apply to the “st,stm32h7-rcc” compatible.
Name |
Type |
Details |
|---|---|---|
|
|
register space
This property is required. See Important properties for more information. |
|
|
indicates the operational status of a device
Legal values: See Important properties for more information. |
|
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compatible strings
This property is required. See Important properties for more information. |
|
|
name of each register space
|
|
|
interrupts for device
See Important properties for more information. |
|
|
extended interrupt specifier for device
|
|
|
name of each interrupt
|
|
|
phandle to interrupt controller node
|
|
|
Human readable string describing the device (used as device_get_binding() argument)
See Important properties for more information. |
|
|
Clock gate information
|
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|
name of each clock
|
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|
number of address cells in reg property
|
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number of size cells in reg property
|
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|
DMA channels specifiers
|
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Provided names of DMA channel specifiers
|
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IO channels specifiers
|
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Provided names of IO channel specifiers
|
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mailbox / IPM channels specifiers
|
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|
Provided names of mailbox / IPM channel specifiers
|
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|
Property to identify that a device can be used as wake up source.
When this property is provided a specific flag is set into the
device that tells the system that the device is capable of
wake up the system.
Wake up capable devices are disabled (interruptions will not wake up
the system) by default but they can be enabled at runtime if necessary.
|
|
|
Power domain the device belongs to.
The device will be notified when the power domain it belongs to is either
suspended or resumed.
|
Specifier cell names
clock cells: bus, bits