If you need urgent consulting help click here
st,stm32-rcc
Vendor: STMicroelectronics
Description
STM32 Reset and Clock controller node.
This node is in charge of system clock ('SYSCLK') source selection and controlling
clocks for AHB (Advanced High Performance) and APB (Advanced Peripheral) bus domains.
Configuring STM32 Reset and Clock controller node:
System clock source should be selected amongst the clock nodes available in "clocks"
node (typically 'clk_hse, clk_hsi', 'pll', ...).
Core clock frequency should also be defined, using "clock-frequency" property.
Note:
Core clock frequency = SYSCLK / AHB prescaler
Last, peripheral bus clocks (typically PCLK1, PCLK2) should be configured using matching
prescaler properties.
Here is an example of correctly configured rcc node:
&rcc {
clocks = <&pll>; /* Select 80MHz pll as SYSCLK source */
ahb-prescaler = <2>;
clock-frequency = <DT_FREQ_M(40)>; /* = SYSCLK / AHB prescaler */
apb1-presacler = <1>;
apb2-presacler = <1>;
}
Specifying a gated clock:
To specify a gated clock, a peripheral should define a "clocks" property encoded
in the following way:
... {
...
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
...
}
After the phandle referring to rcc node, the first index specifies the registers of
the bus controlling the peripheral and the second index specifies the bit used to
control the peripheral clock in that bus register.
Specifying an alternate clock source:
Specifying an alternate source clock could be done by adding a clock specifier to the
clock property:
... {
...
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>,
<&rcc STM32_SRC_HSI I2C1_SEL(2)>;
...
}
In this example I2C1 device is assigned HSI as clock source.
It is device driver's responsibility to querry and use clock source information in
accordance with clock_control API specifications.
Properties
Properties not inherited from the base binding file.
Name |
Type |
Details |
|---|---|---|
|
|
Number of items to expect in a Clock specifier
This property is required. Constant value: |
|
|
default frequency in Hz for clock output
This property is required. |
|
|
AHB prescaler. Defines actual core clock frequency (HCLK)
based on system frequency input.
The HCLK clocks CPU, AHB, memories and DMA.
This property is required. Legal values: |
|
|
This property is required. Legal values: |
|
|
This property is required. Legal values: |
|
|
On some parts, it could be required to set up highest core frequencies
(>80MHz) in two steps in order to prevent undershoot.
This is done by applying an intermediate AHB prescaler before switching
System Clock source to PLL. Once done, prescaler is set back to expected
value.
|
Deprecated properties not inherited from the base binding file.
(None)
Properties inherited from the base binding file, which defines common properties that may be set on many nodes. Not all of these may apply to the “st,stm32-rcc” compatible.
Name |
Type |
Details |
|---|---|---|
|
|
register space
This property is required. See Important properties for more information. |
|
|
indicates the operational status of a device
Legal values: See Important properties for more information. |
|
|
compatible strings
This property is required. See Important properties for more information. |
|
|
name of each register space
|
|
|
interrupts for device
See Important properties for more information. |
|
|
extended interrupt specifier for device
|
|
|
name of each interrupt
|
|
|
phandle to interrupt controller node
|
|
|
Human readable string describing the device (used as device_get_binding() argument)
See Important properties for more information. |
|
|
Clock gate information
|
|
|
name of each clock
|
|
|
number of address cells in reg property
|
|
|
number of size cells in reg property
|
|
|
DMA channels specifiers
|
|
|
Provided names of DMA channel specifiers
|
|
|
IO channels specifiers
|
|
|
Provided names of IO channel specifiers
|
|
|
mailbox / IPM channels specifiers
|
|
|
Provided names of mailbox / IPM channel specifiers
|
|
|
Property to identify that a device can be used as wake up source.
When this property is provided a specific flag is set into the
device that tells the system that the device is capable of
wake up the system.
Wake up capable devices are disabled (interruptions will not wake up
the system) by default but they can be enabled at runtime if necessary.
|
|
|
Power domain the device belongs to.
The device will be notified when the power domain it belongs to is either
suspended or resumed.
|
Specifier cell names
clock cells: bus, bits